Everyone who stays on line till the end of the session will get a link to 2 white papers covering SoC Interconnect performance analysis and functional verification
Our experts are ready to discuss issues relating to performance analysis and functional verification of SoCs containing advanced interconnect IP.
Steve, can you give some examples of what is meant by “interconnect IP”?
Steve has a technical glitch…
There is no video, but this chat stream will be saved on the web site
Avi, since Steve is having a problem, could you tell us what is meant by
"interconnect IP"?
Sure Tom. Interconnect IP is the glue that connects the cores and IP blocks within an SoC. In the old days we just used busses, but now advanced SoCs require special IP to perform the on-chip communication function. People use different names for this IP: “network-on-chip”, “system IP”, or simply “interconnect”
For example, here’s an ARM diagram showing their interconnect IP components.
Interteresting, there's a lot going on here
In the center of this diagram we see the CoreLink CCI-400 Cache Coherent Interconnect. This IP is typically used in multi-core SoCs that implement cache-coherency rules
In the upper-right and lower-right corners of the diagram you can see the NIC-400 IP. That provides interconnect support for non-coherent subsystems and peripherals
So what kind of issues do people run into when designing multi-core SoCs?
There are 2 big issues getting this all to work right: functional verification and performance verification
There are two types of cache relating to interconnect
For L2 typically ACE is used to share multiple L2 caches
In some new ARM interconnects like CCN-504 there is also an L3 cache inside the interconnect
Take a look at the ARM Connected COmmunity web site for some great resources
Avi, you were going to talk about functional and performance verification…
Function verification is making sure the chip implements the desired functionality and handles errors gracefully. Most people are familiar with this
Performance verification is very important but less-well understood. Basically, this means verifying that the design will meet the bandwidth and latency expectations for the design
Avi, help us understand the first issue – functional verification.
Functional verification of the interconnect is a bit of a misnomer. What people want to do is verify the SoC IP blocks *together* with the interconnect
This involves 2 steps: 1) verifying that the IP blocks implement the given interface protocol correctly, and 2) verifying that commands and data arrive at the proper destination and in the right format
These figures illustrates the concept...
First, here’s a simplified block diagram of a theoretical SoC
To verify that each IP component follows the right communication protocol, you can insert verification IP (VIP) components to check for protocol violations. Conceptually, it would look like this…
In this example there are different VIP used for each protocol in the SoC. In this case they are all AMBA protocols: AXI, AHB, ACE, etc
These VIP component monitor simulation results and flag any protocol violations
Avi, that’s important, but like you said, it’s just the first step. The next step is verifying that commands and data pass through the interconnect properly and end up in the right place. For that, we need another VIP component. We call our product the Interconnect Validator…
The Interconnect Validator collects all the transactions and checks for things like data splitting, upsizing, and downsizing. It supports various addressing schemes (FIXED, ICR, WRAP) and is able to resolve ambiguous scenarios such as multiple masters accessing the same slave at the same address at the same time.
For coherent interconnects, these types of operations are checked: verification of snoop conversions, snoop propagation, snoop filter operation, checking of cross-cache line operations, basically making sure that the cache-coherent interconnect performs its role as the Coherency Manager correctly.
The combination of interface VIP and Interconnect Validator help people to fully verify their SoCs
Thanks! Now let’s get back to performance verification. Nick, help us understand why performance verification is so important.
God question, who wants to answer?
the answer is yes, and yes
Everyone who stays on line till the end of the session will get a link to 2 white papers covering SoC Interconnect performance analysis and functional verification
Sure Tom. Interconnect IP is the glue that connects the cores and IP blocks within an SoC. In the old days we just used busses, but now advanced SoCs require special IP to perform the on-chip communication function. People use different names for this IP: “network-on-chip”, “system IP”, or simply “interconnect”
There are two types of cache relating to interconnect
Avi, that’s important, but like you said, it’s just the first step. The next step is verifying that commands and data pass through the interconnect properly and end up in the right place. For that, we need another VIP component. We call our product the Interconnect Validator…
